Tesla announces mass production of wafer-level Dojo processors for AI training

At the recent TSMC North American Technology Seminar, Tesla announced that its wafer-level Dojo processor for artificial intelligence training has begun mass production and is expected to be put into use soon. This processor, called Dojo Training Tile, adopts a 5x5 array layout, contains a total of 25 chips, and is based on a 7nm process technology. TSMC uses its integrated fan-out (InFO) technology and wafer-level interconnect (InFO_SoW) technology to enable these 25 chips to work together like a single processor. In addition, in order to maintain the consistency of wafer-level processors, TSMC also uses virtual chips to fill the gaps between chips. It is expected that by 2027, through CoWoS advanced packaging technology, these wafer-level systems will be able to be integrated into complete wafers, thereby providing up to 40 times the computing power. Tesla's Dojo processor has extremely high performance, but it also brings huge energy consumption, so it requires a complex cooling system and voltage regulation module to meet its power supply needs. Although Tesla has not yet announced the specific performance indicators of the Dojo wafer system, considering the challenges it faces during the research and development process, it is expected to become a powerful artificial intelligence training solution.